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ISL6174
Data Sheet December 19, 2008 FN6830.0
Dual Low Voltage Circuit Breaker
This IC targets dual voltage hot swap applications across the +2.5V to +3.3V (nominal) bias supply voltage range with a second lower voltage rail down to less than 1V where a circuit breaker response to an over current event is preferred. It features a charge pump for driving external N-Channel MOSFETs, accurate programmable circuit breaker current thresholds and delay output undervoltage monitoring and reporting and adjustable soft-start. The circuit breaker current level (ICB) for each rail is set by two external resistors, and for each rail a delay (tCB) is set by an external capacitor on the TCB pin. After tCB has expired, the IC then quickly pulls down the associated GATE(s) output turning off its external FET(s).
Features
* Fast Circuit Breaker Quickly Responds to Overcurrent Fault Conditions * Less than 1s Response Time to Dead Short * Programmable Circuit Breaker Level and Delay * Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions * Overcurrent Circuit Breaker and Fault Isolation Functions * Adjustable Circuit Breaker Threshold as Low as 20mV * Adjustable Voltage Ramp-up for In-Rush Protection During Turn-On * Rail Independent Control, Monitoring and Reporting I/O * Dual Supply Hot Swap Power Distribution Control to <1V * Charge Pump Allows the Use of N-Channel MOSFETs
Ordering Information
PART NUMBER (Note) ISL6174IRZ* PART MARKING ISL6174 IRZ TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
-40 to +85 28 Ld 5x5 QFN L28.5x5
* QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package Footprint, Which Improves PCB Efficiency and has a Thinner Profile * Pb-Free (RoHS Compliant)
ISL617XEVAL1Z Evaluation Platform *Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* Power Supply Sequencing, Distribution and Control * Hot Swap / Electronic Circuit Breaker Circuits
V1(IN) RSET1 RSNS1 V1(OUT)
Pinout
ISL6174 (28 LD QFN) TOP VIEW
OCREF EN2 UV1 EN1 UV2 VS1 VS2
28 27 26 25 24 23 22 SNS1 1 VO1 2 SS1 3 GT1 4 FLT1 5 PG1 6 TCB1 7 8 DNC 9 GND 10 11 12 13 14 CPQ+ CPVDD PGND CPQBIAS 21 SNS2 20 VO2 19 SS2 18 GT2 17 FLT2 16 PG2 15 TCB2 V2(IN)
SNS1 GT1 VO1 UV1 PG1 BIAS FLT1 CPQ+ SS1 CPQOCREF ISL6174 CPVDD SS2 FLT2 PG2 PGND GND UV2 TCB1 TCB2 VS2 SNS2 GT2 VO2 RSET2
EN1 EN2 VS1
V2(OUT) RSNS2
FIGURE 1. TYPICAL APPLICATION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6174 Block Diagram
Io Vin Rsns Iset Rset Q Vo LOAD
SNS1
GT1
Current Limit Amplifier +
10V 24A Soft Start Amplifier 10A
VO1 CPVDD
VS1
42A
SS1 +
1k 3K
+
Css
WOC Comparator OC Timer & Logic
FLT1
1.178V
+ OC Comparator
Iref
OCREF Rref Current Mirror
CPVDD 10A PG1
Iref 4
BIAS 10K EN1
+ -
CT1 TCB1
tCB1
Ct
Timeout Comparator BIAS 10K
1.178V Rs1 633mV UV1
UV + Comparator
RTR/LTCH
BIAS
Rs2
CPQ+ Cp CPQCPVDD Cv POR and Bandgap X2 Charge Pump X2 Charge Pump
10V(out)
633mV
1.178V PGND GND
ISL6173
FIGURE 2. ISL6174 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY
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FN6830.0 December 19, 2008
ISL6174 Pinout
28 LEAD QFN TOP VIEW
OCREF EN2 UV1 EN1 UV2 23 VS1 VS2 22 21 20 19 18 17 16 15 8 DNC 9 GND 10 PGND 11 CPQ12 BIAS 13 CPQ+ 14 CPVDD SNS2 VO2 SS2 GT2 FLT2 PG2 TCB2
28 SNS1 VO1 SS1 GT1 FLT1 PG1 TCB1 1 2 3 4 5 6 7
27
26
25
24
Pin Descriptions
PIN 1 NAME SNS1 FUNCTION Current Sense Input DESCRIPTION This pin is connected to the current sense resistor and control MOSFET Drain node. It provides current sense signal to the internal comparator in conjunction with VS1 pin. This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this voltage is used for SS control. A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by the internal 10A current source setting the soft-start ramp. The output voltage ramp tracks the SS ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and the capacitor to GND from the connection) then both the outputs track each other as they ramp up. Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to 4 X Vbias or 10V(max) from the 24A source. This is an open drain output. It asserts (pulls low) once the circuit breaker delay (determined by the TCB timeout cap) has expired. This output is valid for Vbias>1V. This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V. A capacitor from this pin to ground sets the delay from the onset of an over current event to channel shutdown (circuit breaker delay). Once the voltage on TCB cap reaches VCT_Vth the GATE output is pulled down and the FLT is asserted. The time for circuit breaker delay (tCB) = (CTCB*1.178)/10A. Do not connect This pin is also internally shorted to the metal tab at the bottom of the IC. Charge pump ground. Both GND and PGND must be tied together externally. Charge Pump Capacitor Flying cap lowside. Low Side
2
VO1
Output Voltage 1
3
SS1
Soft-Start Duration Set Input
4
GT1
Gate Drive Output
5
FLT1
Fault Output
6
PG1
Power Good Output
7
TCB1
Circuit Breaker Delay Timer
8 9 10 11
DNC GND PGND CPQ-
Do not connect Chip Gnd
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ISL6174 Pin Descriptions (Continued)
PIN 12 NAME BIAS FUNCTION Chip Bias Voltage DESCRIPTION Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
13
CPQ+
Charge Pump Capacitor Flying cap highside. Use of 0.1F for 2.5V bias and 0.022F for 3.3V bias is recommended. High Side Charge Pump Output This is the voltage used for some internal pull-ups and bias. Use of 0.47F (minimum) is recommended. Same function as pin 7 Same function as pin 6 Same as pin 5 Same as pin 4 Same as pin 3
14
CPVDD
15 16 17 18 19
TCB2 PG2 FLT2 GT2 SS2
Timer Capacitor Power Good Output Fault Output Gate Drive Output Soft-Start Duration Set Input Output Voltage 2 Current Sense Input Current Sense Reference Undervoltage Monitor Input
20 21 22
VO2 SNS2 VS2
Same as pin 2 Same as pin 1 Voltage input for one of the two voltages. Provides a 20A current source for the ISET series resistor which sets the voltage to which the sense resistor IR drop is compared. This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV reference. It is meant to sense the output voltage through a resistor divider. If the output voltage drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted. This is an active low input. When asserted (pulled low), the SS and gate drive are released and the output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens. Allows adjustment of the reference current through RSET and the internal Circuit Breaker set resistor, thus setting the thresholds for CR, OC and WOC. Same as pin 24 Same as pin 23
23
UV2
24
EN2
Enable
25
OCREF
Ref. Current Adj.
26 27
EN1 UV1
Enable Input Undervoltage Monitor Input Current Sense Reference
28
VS1
Same as pin 22
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ISL6174
Absolute Maximum Ratings
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +12V ENx, SNSx, PGx, FLTx, VSx, TCBx, UVx, SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
Thermal Information
Thermal Resistance (Typical, Notes 1, 4) JA (C/W) JC (C/W) 5x5 QFN Package . . . . . . . . . . . . . . . . 42 12.5 Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C For recommended soldering conditions, see Tech Brief TB389. (QFN - Leads Only) Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VBIAS / VIN1 Supply Voltage Range. . . . . . . . . . . +2.25V to +3.63V Temperature Range (TA) -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. All voltages are relative to GND, unless otherwise specified. 3. 1V (min) on the BIAS pin required for FLT to be valid. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside..
Electrical Specifications
VDD = 2.5V to +3.3V, VS = 1V,TA = TJ = -40C to +85C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER CIRCUIT BREAKER CONTROL ISET Current Over Current Comparator Offset Voltage Circuit Breaker Threshold Voltage TCB Threshold Voltage TCB Charging Current TCB Default Delay GATE DRIVE GATE Response Time from WOC (Open)
ISET Vio VCRVTH VCT_Vth ICT TCT
ROCREF = 14.7k VVS - VSNS with IOUT = 0A VVS - VSNS at FLT assertion, RISET = 1.0k, ISET = 20A Peak Voltage
19 -1.25
20 -0.05 19.7
21 1.25
A mV mV
1.128 9
1.178 10 3
1.202 11
V A s
TCB = Open
pd_woc_open
GATE open 100mV of overdrive on the WOC comparator GATE = 1nF 100mV of overdrive on the WOC comparator GATE = 2V, VVS = 2V, VSNS = 2.1V OC or WOC Turn-off Gate Current Bias = 2.5V (Figure 5, 6) 2.1 < Bias < 2.5 (Figure 5, 6) 8.2 21
3
ns
GATE Response Time from WOC (Loaded) GATE Turn-On Current GATE Turn-Off Current GATE Voltage
pd_woc_load
100
ns
IGATE_on IGATE_off VGATE
24 100 8.8 7
27
A mA
9.3
V V
BIAS Supply Current POR Rising Threshold POR Falling Threshold POR Threshold Hysteresis IBIAS VIN_POR_L2H VIN_POR_H2L VIN_POR_HYS VBIAS = 3.3V 6 1.85 1.80 5 9.3 2.02 1.98 33 12 2.12 2.10 mA V V mV
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ISL6174
Electrical Specifications
VDD = 2.5V to +3.3V, VS = 1V,TA = TJ = -40C to +85C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER I/O Undervoltage Comparator Falling Threshold Undervoltage Comparator Hysteresis EN Rising Threshold EN Falling Threshold EN Hysteresis PG Pull-Down Voltage FLT Pull-Down Voltage (Note 3) Soft-Start Charging Current CHARGE PUMP CPVDD CPVDD
VUV_VTHF VUV_HYST PWR_Vth_R PWR_Vth_F PWR_HYST
VOL_PG VOL_FLT
620 9 VBIAS = 2.5V VBIAS = 2.5V VBIAS = 2.5V IPG = 8mA IFLT = 8mA VSS = 1V 1.75 0.97 600 0.05 0.05 9
635 17 2.04 1.11 905 0.15 0.15 10
650 25 2.25 1.20 1175 0.3 0.3 11
mV mV V V mV V V A
ISS
V_CPVDD V_CPVDD
VBIAS = 3.3V VBIAS = 3.3V T = +25C External User Load = 6mA
4.9
5.2 5.0
5.5
V V
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ISL6174 Typical Performance Curves (at +25C unless otherwise specified)
12 NORMALIZED I BIAS CPQ = 22nF, CPVDD = 0.47F 0 1.0 1.4 1.7 2.0 2.3 2.9 3.2 3.7 10 8 I_BIAS (mA) 6 4 2 1.04 1.02 1.00 0.98 0.96 0.94 -40 V_BIAS(V) 0 25 70 85 125 TEMPERATURE (C)
FIGURE 3. I_BIAS vs V_BIAS
FIGURE 4. NORMALIZED I BIAS (VBIAS = 3.3V) vs TEMPERATURE
12.0 10.0 VGATE (V) 8.0 6.0 4.0 2.0 0.0 2.0 CPQ = 0.1F, CPVDD = 0.47F
12.0 10.0 VGATE (V) 8.0 6.0 4.0 2.0 0.0 2.0 CPQ = 22nF, CPVDD = 0.47F
2.2
2.4
2.6
3.8
3.0
3.2
3.4
3.6
3.8 4.0
2.2
2.4
2.6
3.8
3.0
3.2
3.4
3.6
3.8 4.0
V BIAS (V)
V BIAS (V)
FIGURE 5. VGATE vs V_BIAS
GATE TURN_ CURRENT (A) ON 25.0 24.8 24.6 24.4 24.2 24.0 23.8 23.6 23.4 23.2 23.0 -40 TEMPERATURE (C)
FIGURE 6. VGATE vs V_BIAS
9.2 VGATE VBIAS = 2.5V (V) 9.0 8.8 8.6 8.4 8.2 8.0 -40 0 25 70 85 125
0
25
70
85
125
TEMPERATURE (C)
FIGURE 7. GATE VOLTAGE vs TEMPERATURE
FIGURE 8. GATE TURN-ON CURRENT vs TEMPERATURE
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FN6830.0 December 19, 2008
ISL6174 Typical Performance Curves (at +25C unless otherwise specified)
NORMALIZED CIRCUTI BREAKER GATE CURRENT 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 0 25 70 85 125 TEMPERATURE (C) CIRCUIT BREAKER Vth (mV)
(Continued)
25 23 21 19 17 ISET = 20A, RSET = 1.0k 15 13 -40 0 25 70 85 125
TEMPERATURE (C)
FIGURE 9. CIRCUIT BREAKER GATE TURN-OFF CURRENT vs TEMPERATURE
660
FIGURE 10. CIRCUIT BREAKER Vth vs TEMPERATURE
21.00 I SET W ROCREF = 14.7k (A) 20.80 20.60 20.40 20.20 20.00 19.80 19.60 19.40 19.20 19.00 -40 0 25 70 85 125 -40 0 25 70 85 125 TEMPERATURE (C) TEMPERATURE (C)
UNDERVOLTAGE VTH (MV)
655 650 645 640 635 630 625 620 FALLING VTH RISING VTH
FIGURE 11. UNDERVOLTAGE Vth vs TEMPERATURE
FIGURE 12. ISET vs TEMPERATURE
3.0 2.5
10000
TRESPONSE (ns)
1000
RESPONSE TIME (s)
2.0 1.5 1.0 0.5
100
10
1 0 0.1 0.47 1.0 2.0 CG (nF) 4.0 8.7 14 22
0 100
150
200 OC (% OF LIMIT)
250
300
FIGURE 13. WOC RESPONSE vs LOAD CAPACITANCE
FIGURE 14. RESPONSE TIME vs IO*RSNS
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FN6830.0 December 19, 2008
ISL6174 Detailed Description of Operation
ISL6174 targets dual voltage hot-swap applications with a bias of 2.1V to 3.6VDC and the voltages being controlled down to 0.7VDC. The IC's main functions are to control startup inrush current and provide circuit breaker protection of the sourcing supplies from OC loads. This is achieved by enhancing an external MOSFET in a controlled manner. In order to fully enhance the MOSFET, the IC must provide adequate gate to source voltage, which is typically 5V or greater. Hence, the final steady-state voltage on Gate (GT) pin must be a minimum of 5V above the load voltage. Two internal charge-pumps allow this to happen.
VIN Q VO
(SNS) and voltage set (VS) pins. The latter is through a resistor, RSET, as shown. Two levels of overcurrent detection are available to protect against all possible fault scenarios. These levels are: * Timed Circuit Breaker (CB) * Way Overcurrent Circuit Breaker (WOC) Each of these modes is described in detail as follows: TIMED CIRCUIT BREAKER (CB) MODE When the load current reaches the Circuit Breaker threshold (ICB) the ISL6174 enters the timed Circuit Breaker Mode. When the circuit enters this mode, the OC comparator which directly looks at the voltage drop across RSNS detects it and starts the CB delay timer. TCB begins to charge whatever capacitance is on that pin from an internal 10A current source. The amount of time it takes for this capacitance to charge to ~1.18V (VCT_Vth) sets up the Circuit Breaker delay. Upon expiration of the CB delay (tCB), the MOSFET gate is pulled down quickly. If during and prior to tCB expiring the load current falls below ICB then in that case, the Circuit Breaker mode is no longer active and the IC discharges the CTCB cap. The Circuit Breaker threshold (ICB) is set by sinking a reference current, ISET, through RSET by selecting an appropriate resistor between OCREF and GND, which sets IREF. The relationship between IREF and ISET is IREF = 4*ISET, where IREF = Vocref/Rocref = 1.178/Rocref. IREF would typically be set at 80A. This ISET * RSET voltage is then compared to the voltage across a load current series sense low ohmic resistor. Selecting appropriate values for RSET and RSNS such that when IO = ICR,
Io*RSNS = ISET*RSET (EQ. 1)
VO1
GT1
VIN 10V 24A SOFTSTART AMPLIFIER 42A CPVDD + 10A 0 SS1 + 0 CPVDD
FIGURE 15. SOFT-START OPERATION
Controlled Soft-Start
The output voltages are monitored through the Vo pins and slew up at a rate determined by the capacitors on the Soft-start (SS) pin, as illustrated in Figure 15. 24A of gate charge current is available. The soft-start amplifier controls the output voltage by robbing some of the gate charge current thus slowing down the MOSFET enhancement. When the load voltage reaches its set level, as sensed by its respective UV pin through an external resistor divider, the Power Good (PG) output goes active.
WAY OVERCURRENT CIRCUIT BREAKER (WOC) MODE This mode is designed to handle very fast, very low impedance shorts on the load side, which can result in very high di/dt transients on the input current. The WOC circuit breaker level is typically 200% of the Circuit Breaker limit. In this mode the comparator, which directly looks at the voltage drop across RSNS and once the WOC level is exceeded the IC pulls the gate very quickly to GND, the SSx capacitor is discharged, FLT is asserted and a new SS sequence is allowed to begin after ENx recycle.
Current Monitoring and Circuit Breaker Protection
The IC monitors the load current (Io) by sensing the voltage-drop across the low value current sense resistor (RSNS), which is connected in series with the MOSFET (as shown in the "Block Diagram" on page 2), through Sense
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ISL6174
Io VIN + ISET RSET + Rsns Q VO
7. If the load current on the output exceeds the set current limit for greater than the circuit breaker delay, FLT gets asserted and the channel shutdown occurs. 8. If the voltage on UV pin exceeds 633mV threshold as a result of rising Vo, the Power Good (PG) output goes active. 9. At the end of the SS interval, the SS cap voltage reaches CPVDD and remains charged as long as EN remains asserted or there is no other fault condition present that would attempt to pull down the gate.
SNS1
VS1
OC COMPARATOR ISL6174 + 3k + 25 WOC COMPARATOR
GT1 GATE PULLDOWN CURRENT
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for this section, which provides guidelines to select the external component values.
MOSFET (Q1)
This component should be selected on the basis of its rDS(ON) specification at the expected Vgs (gate to source voltage) and the effective input gate capacitance (Ciss). One needs to ensure that the combined voltage drop across the Rsense and rDS(ON) at the desired maximum current (including transients) will still keep the output voltage above the minimum required level. Ciss of the MOSFET influences the overcurrent response time. It is recommended that a MOSFET with Ciss of less than 10nF be chosen. Ciss will also have an impact on the SS cap value selection as seen later.
FIGURE 16. OC / WOC OPERATION
Bias and Charge Pump Voltages:
The BIAS pin feeds the chip bias voltage directly to the first of the two internal charge pumps, which are cascaded. The output of the first charge pump, in addition to feeding the second charge pump, is accessible on the CPVDD pin. The voltage on the CPVDD pin is approximately 5V. It also provides power to the POR and band-gap circuitry as shown in the block diagram. A capacitor connected externally across CPQ+ and CPQ- pins of the IC is the "flying" cap for the charge-pump. The second charge-pump is used exclusively to drive the gates of the MOSFETs during soft start through the 24A current sources, one for each channel. The output of this charge pump is approximately 10V as shown in the "Block Diagram" on page 2.
Current Sense Resistor (RSNS)
The voltage drop across this resistor, which represents the load current (Io), is compared against the set threshold of the Circuit Breaker comparator. The value of this resistor is determined by how much combined voltage drop is tolerable between the source and the load. It is recommended that at least 20mV drop be allowed across this resistor at max load current. This resistor is expected to carry maximum full load current indefinitely. Hence, the power rating of this resistor must be greater than IO(MAX)2*RSNS. This resistor is typically a low value resistor and hence the voltage signal appearing across it is also small. In order to maintain high current sense accuracy, current sense trace routing is critical. It is recommended that either a four wire resistor or the routing method as shown in Figure 17 be used.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first charge pump immediately powers up. 2. If the BIAS voltage is 2.1V or higher, the IC comes out of POR. Both SS and TCB caps remain discharged and the gate (GT) voltage remains low. 3. ENx pin, when pulled below it's specified threshold, enables the respective channel. 4. SSx cap begins to charge up through the internal 10A current source, the gate (GT) voltage begins to rise and the corresponding output voltage begins to rise at the same rate as the SS cap voltage. This is tightly controlled by the soft-start amplifier shown in the block diagram. 5. SS cap begins to charge but the corresponding TCBx cap is held discharged. 6. Fault (FLT) remains deasserted (stays high) and the output voltage continues to rise. 10
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ISL6174
Time-out Capacitor Selection (CT)
LOAD CURRENT CARRYING TRACES
This capacitor determines the current regulation delay period. As shown in Figure 2, when the voltage across this capacitor exceeds 1.178V, the time-out comparator detects it and the gate voltage is pulled to 0V thus shutting down the channel. An internal 10A current source charges this capacitor. Hence, the value of this capacitor is determined by Equation 2.
C T = ( 10A * T OUT ) 1.178 (EQ. 2)
CURRENT SENSE TRACES
RSNS
Where,
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR PCB LAYOUT
TOUT = Desired time-out period.
Soft-Start Capacitor Selection (CSS) Current Set Resistor (RSET)
This resistor sets the threshold for the Circuit Breaker comparator in conjunction with RSNS. Once RSNS has been selected, use Equation 1 to calculate RSET. Use 20A for ISET in a typical application. The rate of change of voltage (dv/dt) on this capacitor, which is determined by the internal 10A current source, is the same as that on the output load capacitance. Hence, the value of this capacitor directly controls the inrush current amplitude during hot swap operation.
C SS = C O * ( 10A I INRUSH ) (EQ. 3)
Reference Current Set Resistor (RREF)
This resistor sets up the current in the internal current source, IREF/4, shown in Figure 2 for the comparators. The voltage at the OCREF pin is the same as the internal bandgap reference. The current (IREF) flowing through this resistor is simply: IREF = 1.178/RREF This current, IREF, should be set at 80A to force 20A in the internal current source as shown in Figure 2, because of the 4:1 current mirror. This equates to the resistor value of 14.7k.
Where, CO = Load Capacitance IINRUSH = Desired Inrush Current IINRUSH is the sum of the DC steady-state load current and the load capacitance charging current. If the DC steady-state load remains disabled until after the soft-start period expires (PGx could be used as a load enable signal, for example), then only the capacitor charging current should be used as IINRUSH. The Css value should always be more than (1/2.4) of that of Ciss of the MOSFET to ensure proper soft-start operation. This is because the Ciss is charged from 24A current source, whereas the Css gets charged from a 10A current source (Figure 15). In order to make sure both VSS and VO track during the soft-start, this condition is necessary.
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator detects the undervoltage condition when it sees the voltage at UV pin drop below 0.633V. The resistor divider values should be selected accordingly.
Charge Pump Capacitor Selection (CP and CV)
CP is the "flying cap" and CV is the smoothing cap of the charge pump, which operates at 450kHz set internally. The output resistance of the charge pump, which affects the regulation, is dependent on the CP value and its ESR, charge-pump switch resistance, and the frequency and ESR of the smoothing cap, CV. It is recommended that CP be kept within 0.022F (minimum) to 0.1F (maximum) range. Only ceramic capacitors are recommended. Use 0.1F cap if CPVDD output is expected to power an external circuit, in which case the current draw from CPVDD must be kept below 10mA. CV should at least be 0.47F (ceramic only). Higher values may be used if low ripple performance is desired.
ISL6174 Evaluation Platform
The ISL617XEVAL1Z is the primary evaluation board for this IC. For the BOM, schematic and photograph, see the "BOM for ISL617XEVAL1Z Board and Schematic" on page 15. The evaluation board has been designed with a typical application in mind and with accessibility to all the featured pins to enable a user to understand and verify these features of the IC. The two circuit breaker levels are programmed to 2.2A for each input rail but they can easily be scaled up or down by adjusting some component values. There are two input voltages, one for each channel that are switched by a dual N-Channel MOSFET (Q1) to the output connectors.
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FN6830.0 December 19, 2008
ISL6174
Pins SS1 and SS2 of the IC are available as jumper test points so that they can be tied together to achieve concurrent tracking between Vo1 and Vo2. Both the EN inputs must be turned on together to check this function, jumpers are provide to facilitate this. Each channel is preloaded with the resistive load that makes up the UV threshold level. Additional loading can be externally applied as desired. The internal Circuit Breaker amplifier is fast enough to respond to very fast di/dt events. On this board, the timeout capacitor value for side `1' is 0.15F, which corresponds to a timeout period of 17.67ms. The scope shots are taken from the ISL6174EVAL1 to demonstrate the ISL6174s critical operational waveforms. Figure 18 illustrates the circuit breaker operation which will be evident with a slow ramping output current at the programmed 2.2A level, ICB. This mode of operation will be invoked while the OC event is < ~2X the ICB. as shown in Figure 19. Characteristic of this operational mode is the TCB pin ramping to VCB to establish the circuit breaker delay. GATE
FIGURE 19. TRANSIENT TO 3.9A OC CIRCUIT BREAKER OPERATION
GATE
Iin
TCB
The way to confirm WOC mode, is by looking at the TCB pin waveform. If no ramping is seen prior to GATE turn off, then WOC is active. The following waveform in Figure 20 shows WOC operation:
:
GATE
TCB TCB Iin Iin
FIGURE 18. SLOW RAMPING TO 2.2A OC CIRCUIT BREAKER OPERATION
FIGURE 20. WOC CIRCUIT BREAKER OPERATION
Figure 21 is a 200X zoom of a WOC turn-off event and clearly illustrates the lack of any TCB ramping during this WOC event.
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FN6830.0 December 19, 2008
ISL6174
GATE
GATE
TCB
TCB
Iin Iin
FIGURE 21. WOC CIRCUIT BREAKER OPERATION ZOOM
Figure 22 illustrates the GATE response time to an output short. The time from the input current > 2.2A (ICB) to the FET gate being pulled down is ~0.6s. GATE
FIGURE 23. TRANSIENT TO 3.9A OC CIRCUIT BREAKER OPERATION with TCB OPEN
Dual Voltage Tracking During Turn-on
The ISL6174 Dual Circuit Breaker is also designed to provide either concurrent or ratiometric tracking of the two output voltages during turn-on. This capability is critical in providing power to many high value loads. The two channels can be forced to track each other by simply tying their SS pins together and using a common SS capacitor, CSS. In addition, their EN pins also must be tied together. Typical Start-up waveforms in this mode are shown in Figure 24, where the common CSS value is 0.066F.
Iin
VO1
FIGURE 22. SHORTED OUTPUT GATE RESPONSE
The previous scope shots illustrate the performance with a ~18ms circuit breaker delay, tCB as determined by the 10.5F cap on TCB pin. Figure 23 shows the performance with an open TCB pin for the same amplitude of OC event as shown in Figure 19. Once again, see the TCB pin ramp duration and tCB of ~3s, the intrinsic delay of the IC OC response.
VO2
FIGURE 24. CONCURRENT TRACKING MODE
If one channel experiences a CB event and turns off, the other one will too. To achieve ratiometric tracking, the ratio of the two CSS must match the ratio of the two voltages being handled. In the illustrated case in Figure 25, the 1.5V to 3.3V ratio of 1:2.2 is
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FN6830.0 December 19, 2008
ISL6174
reflected in the choices of CSS cap values of 0.033F and 0.072F. These cap values result in the performance demonstrated, the variance from a perfect match being the effect of variance in capacitor values, VSS and ISS.
VO1
VO2
FIGURE 25. RATIOMETRIC TRACKING MODE
ISL617XEVAL1Z Photograph
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6830.0 December 19, 2008
ISL6174 BOM for ISL617XEVAL1Z Board and Schematic
REFERENCE U1 Q1 C1 C2 C7 C3 C5, C9 C6, C11 C10 R7, R13 R1 R16 R10 R3 R4, R5, R14, R15 R8, R12 R2, R6, R17, R18 J_EN1, EN1-2, J_EN2, JRTR_LTCH, SS1_SS2 PART Circuit Breaker IC FDS6912A 0.033F 0.15F 0.47F 2.2F 0.1F 0.022F 0.22F 0.01 3.57k 2.55k 14.7k 0 10k 1.1k 1k Jumper 0402 0402 2512 0402 0402 0402 0402 0402 0402 0402 2 PIN, 0.1" PKG 28 Ld 5X5 QFN SO8 0402 0402 MFG P/N ISL6174DRZ FDS6912A or equivalent MANUFACTURER Intersil Various Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any
ISL6174
ISL6174
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FN6830.0 December 19, 2008
ISL6174
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07
4X 3.0 5.00 A B 6 PIN 1 INDEX AREA 24X 0.50 6 PIN #1 INDEX AREA
22
28 1
21
5.00
3 .10 0 . 15
15
(4X) 0.15 14 8
7
TOP VIEW
28X 0.55 0.10
0.10 M C A B - 0.07 4 28X 0.25 + 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1 BASE PLANE ( 4. 65 TYP ) ( 24X 0 . 50) ( 3. 10)
C
SEATING PLANE 0.08 C
SIDE VIEW
(28X 0 . 25 ) C 0 . 2 REF 5
( 28X 0 . 75)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6830.0 December 19, 2008

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